This invention relates generally to RF power amplifiers, and more particularly the invention relates to a semiconductor field effect transistor having a voltage biased buried shield electrode which provides adjustable linearity in device operation.
A typical RF electrical signal power amplifier has multiple stages including a driver stage and a plurality of output stages connected in parallel. For applications requiring amplification of signals with very high peak to average power requirements, additional amplifier stages must be provided for the peak power without signal clipping. However, this is not an efficient use of silicon and results in poor overall performance and high cost.
Heretofore, circuits have been proposed to give improved amplified linearity with varying signal input power. Kishida U.S. Pat. No. 4,511,854 discloses a circuit which minimizes clipping by boosting linearity as signal peaks are received by the amplifier. However, the proposed linearity correction is a function of output signal and not the input signal.
For best device RF operation, the parasitic capacitances (C.sub.rss, C.sub.oss) and device resistance (R.sub.dson) of devices must be minimized. Optimization of the parameters is typically bounded by certain specifications, for example a minimum breakdown voltage (BV.sub.dss) is typically specified, for example greater than 60 Volts for cellular base station amplifiers. Gate to source capacitance, C.sub.rss, can be minimized by using polycide gate structures which can minimize gate to drain overlap, but the device resistance (R.sub.dson) and transconductance linearity typically degrade due to a limit on the maximum N-well doping for such devices.
Adler et al., U.S. Pat. No. 5,252,848 discloses a field effect transistor device which provides reduced source to drain resistance in RF applications. The structure includes extending the source electrode over a polysilicon gate to provide increased isolation of the gate from the drain and substrate. However, the structure does not reduce the direct capacitance coupling of the gate electrode to the underlying drain.
Weitzel et al. U.S. Pat. No. 5,119,149 discloses a field effect transistor having a gate-drain shield on the device surface to reduce lateral gate-drain capacitance. The device does not shield vertical capacitance of the overlapping gate and drain region.
Lin et al., U.S. Pat. No. 5,243,234 discloses a dual gate field effect transistor in which a second gate is placed on top of the primary gate of a lateral DMOS transistor and is used to modulate conductivity of the channel. However, the device has very high gate to drain capacitance since the second gate is directly over the drain region. Since gate to substrate capacitance is not minimized, the device is not well suited for RF applications.
The present invention is directed to a field effect transistor structure including a shield electrode between the gate and drain regions of the transistor and which can be used as a feedback electrode in providing increased linearity of the device as an RF power amplifier.